VMIVME-7750 VMIVME-7750-734001 350-027750-734001 K VME Single Board Computer GE

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Essential details：VMIVME-7750 VMIVME-7750-734001 350-027750-734001 K VME Single Board Computer GE

Features:
• Up to 1.26 GHz Pentium® III processor with 512 Kbyte advanced transfer cache
• Up to 512 Mbyte PC133 SDRAM using a single SODIMM
• Internal AGP SVGA controller with 4 Mbyte display cache
• 133 MHz system bus via Intel® 815E chipset
• Dual Ethernet controllers supporting 10BaseT and 100BaseTX
• interfaces ting
• ows 2000, VxWorks®, Solaris™, QNX®, LynxOS®, and Linux®
• Remote Ethernet boo
• PMC expansion site Operating system support for Windows® XP, Wind

VMIVME-7750VMIVME-7750

VMEbus Requester: The microprocessor can request and gain control of the bus using any of the VMEbus request lines (BR3* to BR0*) under software control. The requester can be programmed to operate in any of the following modes:
Release-On-Request (ROR)
Release-When-Done (RWD)
VMEbus Capture and Hold (BCAP)
Mailboxes: The VMEbus interface provides four 32-bit mailboxes, which are accessible from both the microprocessor and the VMEbus providing interprocessor communication. The mailboxes have the ability to interrupt the microprocessor when accessed by VMEbus.
Interrupt Handler: The interrupt handler monitors, and can be programmed to respond to any or all VMEbus IRQ* lines. All normal-process VMEbus-related interrupts can be mapped to PCI INTA# or SERR# interrupts. These include:
Mailbox interrupts
VMEbus interrupts
VMEbus interrupter IACK cycle (acknowledgment of VMIVME-7750 VMEbus-issued interrupts) All error processing VMEbus-related interrupts can be mapped to PCI INTA# or SERR#. Note: PCI SERR# initiates a SBC NMI.
These include:
ACFAIL* interrupt
BERR* interrupt
SYSFAIL* interrupt
The interrupt handler has a corresponding STATUS/ID register for each IRQ* interrupt. Once the handler receives an IRQ*, it requests the VMEbus and, once granted, it performs an IACK cycle for that level. Once the IACK cycle is complete and the STATUS/ID is stored in the corresponding ID register, an appropriate interrupt status bit is set in an internal status register, and a PCI interrupt is generated. The PCI interrupt can be mapped to PCI INTA# or SERR#.

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