Description
Overview
Essential details:IS200TRPGH1BDE PRIMARY TRIP TERMINAL BOARD
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IS200TRPGH1BDE PRIMARY TRIP TERMINAL BOARD
Fig 1: TRPG Terminal Board and Cabling
INSTALLATION:
The flame detectors (if utilized) are attached directly to the second terminal block, while the three trip solenoids are wired to the first I/O terminal block. The flame detectors are linked with the power to J3, J4, and J5. J1 receives 125 V dc power for the trip solenoids, and J2 supplies power to the TREG board.
OPERATION:
The main protection solenoids are tripped by the main protection relays on TRPG, which are controlled by the I/O board. In TMR applications, a relay ladder logic two-out-of-three voting circuit is used to vote the three inputs in hardware. The I/O board keeps track of supply voltages for diagnostic purposes and tracks the current flow in its relay driver control line to determine whether to electrify or de-electrify the relay coil contact status. The diagnostics check each normally closed contact from a relay on the TRPG board to make sure it is functioning properly.
Fig 3: TRPG and Connections to Controller and Trip Solenoids
The controller transmits the primary Overspeed trip, which is subsequently transmitted to the I/O pack or board and finally to the TRPG terminal board. Together with the TREG board, which is managed by the VPRO emergency Overspeed system, TRPG functions. The TRPG/TREG combination may drive three ETDs.
DIAGNOSTICS:
The TRPG diagnostics are run by the I/O board. These include feedback from the trip solenoid relay driver and contact, the solenoid power bus, and the excitation voltage for the flame detector being too low or excessive. If any of the signals becomes abnormal, a diagnostic warning is generated (beyond limits). The terminal board’s connectors JR1, JS1, and JT1 each have their own ID device that the I/O board queries. If a discrepancy is found, a hardware incompatibility fault is generated. The terminal board serial number, board type, revision number, and plug location are all encoded on the read-only ID device chip.