VMIVME-7751 VMEbus Single-Board Computer VMIVME-7750

Description

Overview

Essential details：VMIVME-7751 VMEbus Single-Board Computer VMIVME-7750

DESCRIPTION

PMC EXPANSION SITE-The VMIVME-7751provides three 5 VPCI mezzanine card (PMC) expansionsites conforming to lEEE Pl386 common mezzanine cardspecifcation.One expansion site is located on the baseboard and two are located on the expansion board.
Contact VMIC for more information concerning PMCmodules and compatibility.
ON-BOARD IDE DISK DRIVE_An on-boardlocation for either 2.5-inch or 1.8-inch IDE hard disk driveis available as an option. The 2.5-inch hard disk consumesone PMC site, thereby limiting the SBC to two PMC sitesHowever, the 1.8-inch IDE disk drive physical envelope issuch that it does not consume a PMC site, and all sites areavailable for user application.
UNIVERSAL SERIAL BUS(USB)_TheVMIVME-7751 provides a front panel dual connection hubhost controller for the USB. Supported USB features includeisochronous data transfers,asynchronous messaging,self-identifcation and confguration of peripherals, anddynamic (hot) attachment.
VMEbUS INTERFACE_The VMIVME-7751VMEbus interface is based on the Universe llBhigh-performance PCl-to-VME interface fromNewbridge/Tundra.
SYSTEM CONTROLLER -The on-board VMEbussystem controller capabilities allow the board to operate as aslot l controller, or it may be disabled when another board isacting as the system controller. The system controller maybe programmed to provide the following modes
Round Robin (RRS)Single Level (SGL)
Priority (PRI)
The system controller provides a SYSCLK driver,IACK* daisy-chain driver, and a VMEbus access timeouttimer. The system controller also provides an arbitrationtimeout if BBSY* is not seen within a specifed period aftera BGOUT* signal is issued,This period is programmable for16 or 256 us.

VMIVME-7751-760000

Product parameter

APPLICATION

MAILBOXES-The VMEbus interface provides four32-bit mailboxes which are accessible from both themicroprocessor and the VMEbus providing interprocessorcommunication.The mailboxes have the ability to interrupt themicroprocessor when accessed by VMEbus.
INTERRUPT HANDLER – The interrupt handlermonitors, and can be programmed to respond to, any or allVMEbus IRO* lines. All normal-process VMEbus-relatedinterrupts can be mapped to PCI INTA# or SERR#f interruptsThese include:
Mailbox interrupts
VMEbus interrupts
VMEbus interrupter lACk cycle (acknowledgment ofVMIVME-7751 VMEbus-issued interrupts)
All error processing VMEbus-related interrupts can bemapped to PCI INTA# Or SERR#. Note: PCI SERR# initiatesa SBC NMl. These include:
ACFAIL* interrupt
BERR* interruptSYSFAIL* interrupt
The interrupt handler has a corresponding STATUS/IDregister for each lRQ* interrupt. Once the handler receives anIRO*,it requests the VMEbus and, once granted, it performsan lACK cycle for that level. Once the lACK cycle is completeand the STATUS/lD is stored in the corresponding ID registeran appropriate interrupt status bit is set in an internal statusregister and a PCI interrupt is generated, The PCl interrupt canbe mapped to PCI INTA# Or SERR#.
INTERRUPTER-Interrupts can be issued undersoftware control on any or all of the seven VMEbus interruptlines (lRO7* to IROl*).A common ID register is associatedwith all interrupt lines. During the interrupt acknowledgecycle, the interrupter issues the ID to the interrupt handler
The interrupter can be programmed to generate a PClINTA# or SERR# interrupt when a VEbus interrupt handleracknowledges a software-generated VMEbus interrupt.

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